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this is information on a product in full production. october 2013 docid17362 rev 6 1/37 VND5E006ASP-E double channel high-side driver with analog current sense for automotive applications datasheet - production data features ? general ? very low standby current ? 3.0 v cmos compatible inputs ? optimized electromagnetic emissions ? very low electromagnetic susceptibility ? compliance with european directive 2002/95/ec ? very low current sense leakage ? diagnostic functions ? proportional load current sense ? high current sense precision for wide currents range ? current sense disable ? off-state openload detection ? output short to v cc detection ? overload and short to ground (power limitation) indication ? thermal shutdown indication ? protection ? undervoltage shutdown ? overvoltage clamp ? load current limitation ? self limiting of fast thermal transients ? protection against loss of ground and loss of v cc ? overtemperature shutdown with auto restart (thermal shutdown) ? inrush current active management by power limitation ? reverse battery protected with self switch of the powermos ? electrostatic discharge protection applications ? all types of resistive, inductive and capacitive loads description the VND5E006ASP-E is a double channel high-side driver manufactured using st proprietary vipower? m0-5 technology and housed in powerso-16 package. the device is designed to drive 12 v automotive grounded loads, and to provide protection and diagnostics. they also implement a 3 v and 5 v cmos compatible interface for the use with any microcontroller. the device integrates advanced protective functions such as load current limitation, inrush and overload active management by power limitation, overtemperature shut-off with auto restart and overvoltage active clamp. a dedicated analog current sense pin is associated with every output channel providing enhanced diagnostic functions including fast detection of overload and short-circuit to ground through power limitation indication, overtemperature indication, short- circuit to v cc diagnosis and on-state and off-state open-load detection. the current sensing and diagnostic feedback of the whole device can be disabled by pulling the cs_dis pin high to share the external sense resistor with similar devices. max transient supply voltage v cc 41 v operating voltage range v cc 4.5 to 28 v typ on-state resistance (per ch.) r on 5 m current limitation (typ) i limh 100 a off-state supply current i s 2 a (1) 1. typical value with all loads connected. powerso-16 www.st.com
contents VND5E006ASP-E 2/37 docid17362 rev 6 contents 1 block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.2 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.3 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.4 waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.5 electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.1 load dump protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.2 mcu i/os protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.3 current sense and diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.3.1 short to vcc and off-state open-load detection . . . . . . . . . . . . . . . . . . 26 3.4 maximum demagnetization energy (vcc = 13.5 v) . . . . . . . . . . . . . . . . . 27 4 package and pcb thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4.1 powerso-16 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.1 ecopack ? packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.2 powerso-16 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.3 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6 order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
docid17362 rev 6 3/37 VND5E006ASP-E list of tables 3 list of tables table 1. pin function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 table 2. suggested connections for unused and not connected pins . . . . . . . . . . . . . . . . . . . . . . . . 6 table 3. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 4. thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 5. power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 6. switching (v cc = 13 v; t j = 25 c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 7. logic inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 8. protections and diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 9. current sense (8 v < v cc < 18 v). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 10. open-load detection (8 v < v cc < 18 v). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 11. truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 12. electrical transient requirements (part 1/3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 13. electrical transient requirements (part 2/3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 14. electrical transient requirements (part 3/3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 15. thermal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 16. powerso-16 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 17. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 18. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
list of figures VND5E006ASP-E 4/37 docid17362 rev 6 list of figures figure 1. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 2. configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 3. current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 4. current sense delay characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 5. open-load off-state delay timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 6. switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 7. delay response time between rising edge of output current and rising edge of current sense (cs enabled). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 8. output voltage drop limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 9. i out /i sense vs i out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 10. maximum current sense ratio drift vs load current (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 11. normal operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 12. overload or short to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 13. intermittent overload . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 14. off-state open-load with external circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 15. short to v cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 16. t j evolution in overload or short to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 17. off-state output current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 18. high level input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 19. input clamp voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 20. input high level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 21. input low level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 22. input hysteresis voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 23. on-state resistance vs t case . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 24. on-state resistance vs v cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 25. undervoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 26. i limh vs t case . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 27. turn-on voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 28. turn-off voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 29. cs_dis clamp voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 30. low level cs_dis voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 31. high level cs_dis voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 32. application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 33. current sense and diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 34. maximum turn-off current versus inductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 35. powerso-16 pc board (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 36. rthj-amb vs pcb copper area in open box free air condition (one channel on) . . . . . . . . 28 figure 37. powerso-16 thermal impedance junction ambient single pulse (one channel on) . . . . . . 29 figure 38. thermal fitting model of a double channel hsd in powerso-16 (1) . . . . . . . . . . . . . . . . . . 29 figure 39. powerso-16 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 40. powerso-16 tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3 figure 41. powerso-16 tape and reel shipment (suffix ?tr?) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 42. powerso-16 suggested pad layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 4
docid17362 rev 6 5/37 VND5E006ASP-E block diagram and pin description 36 1 block diagram and pin description figure 1. block diagram table 1. pin function name function v cc battery connection. outn power output. gnd ground connection. inn voltage controlled input pin with hysteresis, cmos compatible. controls output switch state. csn analog current sense pin, delivers a current proportional to the load current. cs_dis active high cmos compatible pin, to disable the current sense pin. &rqwuro 'ldjqrvwlf 9 && &+ &rqwuro 'ldjqrvwlf /2*,& '5,9(5 9 21 /l plwdwlrq &xuuhqw /lplwdwlrq 3rzhu &odps 2yhu whps 8qghuyrowdjh &+ 29(5/2$'3527(&7,21 $&7,9(32:(5/,0,7$7,21 ,1 ,1 &6 &6 &6b ',6 *1' 287 287 6ljqdo&odps 5hyhuvh %dwwhu\ 3urwhfwlrq $*9 &xuuhqw 6hqvh 9 6(16(+ )dxow
block diagram and pin description VND5E006ASP-E 6/37 docid17362 rev 6 figure 2. configuration diagram (top view) table 2. suggested connections for unused and not connected pins connection / pin current sense n.c. output input cs_dis floating not allowed x x x x to ground through 1 k resistor x not allowed through 10 k resistor through 10 k resistor 287b &6b',6 *1' 1& 287b ,1b &6b 1& &6b ,1b 9 && 287b 287b 287b 287b 287b 287b $*9
docid17362 rev 6 7/37 VND5E006ASP-E electrical specifications 36 2 electrical specifications figure 3. current and voltage conventions 2.1 absolute maximum ratings stressing the device above the ratings listed in the ?absolute maximum ratings? tables may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. exposure to the conditions in this section for extended periods may affect device reliability. refer also to the stmicroelectronics sure program and other relevant quality documents. 287 ,1 *1' &6b',6 , &6' &6 , ,1 9 ,1 9 &6' , *1' , 6(16( 9 6(16( , 287 , 6 9 && 9 && 9 287 $*9 table 3. absolute maximum ratings symbol parameter value unit v cc dc supply voltage 28 v v ccpk transient supply voltage (t < 400 ms, r load > 0.5 )41v -v cc reverse dc supply voltage 16 v i out dc output current internally limited a -i out reverse dc output current 60 a i in dc input current -1 to 10 ma i csd dc current sense disable input current -1 to 10 ma v csense current sense maximum voltage v cc -41 +v cc v v e max maximum switching energy (single pulse) (l = 1.4 mh; r l = 0 ; v bat = 13.5 v; t jstart = 150 c; i out = i liml (typ.) ) 600 mj
electrical specifications VND5E006ASP-E 8/37 docid17362 rev 6 2.2 thermal data v esd electrostatic discharge (human body model: r = 1.5 k ; c = 100 pf) ? input ? current sense ? cs_dis ? output ?v cc 4000 2000 4000 5000 5000 v v esd charge device model (cdm-aec-q100-011) 750 v t j junction operating temperature -40 to 150 c t stg storage temperature -55 to 150 c table 3. absolute maximum ratings (continued) symbol parameter value unit table 4. thermal data symbol parameter maximum value unit r thj-case thermal resistance junction-case (max) (with one channel on) 0.4 c/w r thj-amb thermal resistance junction-ambient see figure 36 c/w
docid17362 rev 6 9/37 VND5E006ASP-E electrical specifications 36 2.3 electrical characteristics 8 v < v cc < 28 v; -40 c < t j < 150 c, unless otherwise specified. table 5. power section symbol parameter test conditions min. typ. max. unit v cc operating supply voltage 4.5 13 28 v v usd undervoltage shutdown 3.5 4.5 v v usdhyst undervoltage shutdown hysteresis 0.5 v r on on-state resistance i out = 10 a; t j = 25 c 5 m i out = 10 a; t j = 150 c 10 m i out = 10 a; v cc = 5 v; t j = 25 c 8 m r on rev reverse battery on-state resistance v cc = -13 v; i out = -10 a; t j = 25 c 6m v clamp clamp voltage i s = 20 ma 41 46 52 v i s supply current off-state; v cc = 13 v; t j = 25 c; v in = v out = v sense = v csd = 0 v 2 (1) 1. powermos leakage included. 5 (1) a on-state; v cc = 13 v; v in = 5 v; i out = 0 a 3.5 6.5 ma i l(off1) off-state output current (2) 2. for each channel. v in =v out =0v; v cc =13v; t j =25c 0 0.01 3 a v in =v out =0v; v cc =13v; t j =125c 0 5 a table 6. switching (v cc = 13 v; t j = 25 c) symbol parameter test conditions min. typ. max. unit t d(on) turn-on delay time r l = 1.3 (see figure 6 )? 35 ?s t d(off) turn-off delay time r l = 1.3 (see figure 6 )? 20 ?s (dv out /dt) o n turn-on voltage slope r l = 1.3 ? see figure 27 ?v / s (dv out /dt) o ff turn-off voltage slope r l = 1.3 ? see figure 28 ?v / s w on switching energy losses during t won r l = 1.3 (see figure 6 )?2.5?mj w off switching energy losses during t woff r l = 1.3 (see figure 6 )?1.2?mj
electrical specifications VND5E006ASP-E 10/37 docid17362 rev 6 table 7. logic inputs symbol parameter test conditions min. typ. max. unit v il input low level voltage 0.9 v i il low level input current v in = 0.9 v 1 a v ih input high level voltage 2.1 v i ih high level input current v in = 2.1 v 10 a v i(hyst) input hysteresis voltage 0.25 v v icl input clamp voltage i in = 1 ma 5.5 7 v i in = -1 ma -0.7 v v csdl cs_dis low level voltage 0.9 v i csdl low level cs_dis current v csd = 0.9 v 1 a v csdh cs_dis high level voltage 2.1 v i csdh high level cs_dis current v csd = 2.1 v 10 a v csd(hyst ) cs_dis hysteresis voltage 0.25 v v cscl cs_dis clamp voltage i csd = 1 ma 5.5 7 v i csd = -1 ma -0.7 v table 8. protections and diagnostics (1) 1. to ensure long term reliability under heavy overload or short circuit conditions, protection and related diagnostic signals must be used together with a proper so ftware strategy. if the device is subjected to abnormal conditions, this software must limit the duration and number of activation cycles. symbol parameter test conditions min. typ. max. unit i limh dc short circuit current v cc = 13 v 70 100 140 a 5 v < v cc < 24 v 140 a i liml short circuit current during thermal cycling v cc = 13 v; t r < t j < t tsd 25 a t tsd shutdown temperature 150 175 200 c t r reset temperature t rs + 1 t rs + 5 c t rs thermal reset of status 135 c t hyst thermal hysteresis (t tsd -t r ) 7c v demag turn-off output voltage clamp i out = 2 a; v in = 0; l = 6 mh v cc - 28 v cc - 31 v cc - 35 v v on output voltage drop limitation i out =1 a; t j = -40 c...150 c (see figure 8 ) 25 mv
docid17362 rev 6 11/37 VND5E006ASP-E electrical specifications 36 table 9. current sense (8 v < v cc < 18 v) symbol parameter test conditions min. typ. max. unit k 0 i out /i sense i out = 5 a; v sense = 0.5 v t j = -40 c...150 c 8300 12640 17600 k 1 i out /i sense i out = 10 a; v sense = 0.5 v t j = -40 c...150 c t j = 25 c...150 c 9200 9602 13220 13220 17300 16703 dk 1 /k 1 (1) current sense ratio drift i out = 10 a; v sense = 0.5 v; v csd = 0 v; t j = -40 c...150 c -13 13 % k 2 i out /i sense i out = 15 a; v sense = 4 v t j = -40 c...150 c t j = 25 c...150 c 9500 10408 13120 13120 16900 15907 dk 2 /k 2 (1) current sense ratio drift i out = 15 a; v sense = 4 v; v csd = 0 v; t j = -40 c...150 c -10 10 % k 3 i out /i sense i out = 25 a; v sense = 4 v t j = -40 c...150 c t j = 25 c...150 c 10600 11278 12920 12920 15600 14644 dk 3 /k 3 (1) current sense ratio drift i out = 25 a; v sense = 4 v; v csd = 0 v; t j = -40 c...150 c -7 7 % i sense0 analog sense leakage current i out = 0 a; v sense = 0 v; v csd = 5 v; v in = 0 v; t j = -40 c...150 c 01a v csd = 0 v; v in = 5 v; t j = -40 c...150 c 02a i out = 10 a; v sense = 0 v; v csd = v in = 5 v 01a v sense max analog sense output voltage i out = 25 a; v csd = 0 v 5 v v senseh (2) analog sense output voltage in fault conditions v cc = 13 v; r sense = 10 k 8v i senseh (2) analog sense output current in fault conditions v cc = 13 v; v sense = 5 v 7 ma t dsense1h delay response time from falling edge of cs_dis pin v sense < 4 v, 5 a < i out < 25 a i sense = 90 % of i sense max (see figure 4 ) 50 100 s t dsense1l delay response time from rising edge of cs_dis pin v sense < 4 v, 5 a < i out < 25 a i sense = 10 % of i sense max (see figure 4 ) 520s
electrical specifications VND5E006ASP-E 12/37 docid17362 rev 6 t dsense2h delay response time from rising edge of input pin v sense < 4 v, 5 a < i out < 25 a i sense = 90 % of i sense max (see figure 4 ) 110 600 s t dsense2 h delay response time between rising edge of output current and rising edge of current sense v sense < 4v, i sense = 90 % of i sensemax, i out = 90 % of i outmax i outmax =10 (see figure 7 ) 300 s t dsense2l delay response time from falling edge of input pin v sense < 4 v, 5 a < i out < 25 a i sense = 10 % of i sense max (see figure 4 ) 100 250 s 1. parameter guaranteed by design; it is not tested. 2. fault conditions includes: power limitation, overtemperature and open-load off-state detection. table 10. open-load detection (8 v < v cc < 18 v) symbol parameter test conditions min. typ. max. unit v ol open-load off-state voltage detection threshold v in = 0 v, 8 v < v cc < 18 v 2 ? 4 v i ol open-load on-state current detection threshold v in = 5 v, 8 v < v cc < 18 v i sense = 5 a 10 ? 100 ma t dstkon output short circuit to v cc detection delay at turn off see figure 5 180 ? 1200 s i l(off2) off-state output current at v out = 4 v v in = 0 v; v sense = 0 v v out rising from 0 v to 4 v -120 ? 0 a td_vol delay response from output rising edge to v sense rising edge in open-load v in = 0 v; v out = 4 v v sense = 90 % of v senseh ?20s table 9. current sense (8 v < v cc < 18 v) (continued) symbol parameter test conditions min. typ. max. unit
docid17362 rev 6 13/37 VND5E006ASP-E electrical specifications 36 figure 4. current sense delay characteristics figure 5. open-load off-state delay timing figure 6. switching characteristics 6(16(&855(17 ,1387 /2$'&855(17 &6b',6 w '6(16(+ w '6(16(/ w '6(16(/ w '6(16(+ $*9 9 ,1 9 &6 w '67.21 287387678&.$79 && 9 287 !9 2/ 9 6(16(+ $*9 g9 287 gw rq w u w grq ,1387 w w 9 287 w :rq w :rii g9 287 gw rii w i w grii $*9
electrical specifications VND5E006ASP-E 14/37 docid17362 rev 6 figure 7. delay response time between rising edge of output current and rising edge of current sense (cs enabled) figure 8. output voltage drop limitation 9 ,1 , 287 , 6(16(0$; ?w '6(16(+ w w w , 6(16(0$; , 2870$; , 2870$; , 6(16( $*9 9 21 , 287 7 m ?& 7 m ?& 7 m ?& 9 21 5 21 7 9 && 9 287 $*9
docid17362 rev 6 15/37 VND5E006ASP-E electrical specifications 36 figure 9. i out /i sense vs i out figure 10. maximum current sense ratio drift vs load current (1) 1. parameter guaranteed by design; it is not tested. ,rxw,vhqvh ,rxw>$@ $ 0d[7m ?&wr?& ' 0lq7m ?&wr?& % 0d[7m ?&wr?& ( 0lq7m ?&wr?& & 7\slfdo7m ?&wr?& $ % & ' ( $*9 g..>@ ,rxw>$@ $ % $ 0d[7m ?&wr?& % 0lq7m ?&wr?& $*9
electrical specifications VND5E006ASP-E 16/37 docid17362 rev 6 table 11. truth table conditions input output sense (v csd = 0 v) (1) 1. if the v csd is high, the sense output is at a high impedance, its potential depends on leakage currents and external circuit. normal operation l h l h 0 nominal overtemperature l h l l 0 v senseh undervoltage l h l l 0 0 overload h h x (no power limitation) cycling (power limitation) nominal v senseh short circuit to gnd (power limitation) l h l l 0 v senseh open-load off-state (with external pull up) lhv senseh short circuit to v cc (external pull up disconnected) l h h h v senseh < nominal negative output voltage clamp ll0
docid17362 rev 6 17/37 VND5E006ASP-E electrical specifications 36 table 12. electrical transient requirements (part 1/3) iso 7637-2: 2004(e) test pulse test levels (1) 1. the above test levels must be considered referred to v cc = 13.5 v except for pulse 5b. number of pulses or test times burst cycle/pulse repetition time delays and impedance iii iv 1 -75 v -100 v 5000 pulses 0.5 s 5 s 2 ms, 10 2a +37 v +50 v 5000 pulses 0.2 s 5 s 50 s, 2 3a -100 v -150 v 1h 90 ms 100 ms 0.1 s, 50 3b +75 v +100 v 1h 90 ms 100 ms 0.1 s, 50 4 -6 v -7 v 1 pulse 100 ms, 0.01 5b (2) 2. valid in case of external load dump clamp: 40v maximum referred to ground. the protection strategy allows powermos to be cyclically switched on duri ng load dump, so distributing the load dump energy along the time and to transfer a part of it to the load. +65 v +87 v 1 pulse 400 ms, 2 table 13. electrical transient requirements (part 2/3) iso 7637-2: 2004(e) test pulse test level results (1) 1. the above test levels must be considered referred to v cc = 13.5 v except for pulse 5b. iii iv 1c c 2a c c 3a c c 3b c c 4c c 5b (2)(3) 2. valid in case of external load dump clamp: 40v maximum referred to ground. the protection strategy allows powermos to be cyclically switched on duri ng load dump, so distributing the load dump energy along the time and to transfer a part of it to the load. 3. suppressed load dump (pulse 5b) is withstood wi th a minimum load connected as specified in table 3: absolute maximum ratings . cc table 14. electrical transient requirements (part 3/3) class contents c all functions of the device are performed as designed after exposure to disturbance. e one or more functions of the device are not performed as designed after exposure to disturbance and cannot be returned to proper operation without replacing the
electrical specifications VND5E006ASP-E 18/37 docid17362 rev 6 2.4 waveforms figure 11. normal operation figure 12. overload or short to gnd , 287 9 6(16( 9 &6b',6 ,1387 1rplqdoordg 1rplqdoordg 1rupdorshudwlrq $*9 3rzhu/lplwdwlrq , /lp+ ! , /lp/ ! 7khupdof\folqj 2yhuordgru6kruwwr*1' , 287 9 6(16( 9 &6b',6 ,1387 $*9
docid17362 rev 6 19/37 VND5E006ASP-E electrical specifications 36 figure 13. intermittent overload figure 14. off-state open-load with external circuitry ! 1rplqdoordg ,qwhuplwwhqw2yhuordg ! 2yhuordg ! , 287 9 6(16( 9 &6b',6 ,1387 9 6(16(+ , /lp+ , /lp/ $*9 2)) 6wdwh2shq/rdg zlwkh[whuqdoflufxwu\ ! , 287 9 6(16( 9 &6b',6 ,1387 9 287 $*9 9 2/ 9 287 !9 2/ 9 6(16(+ w '67.rq
electrical specifications VND5E006ASP-E 20/37 docid17362 rev 6 figure 15. short to v cc figure 16. t j evolution in overload or short to gnd w '67.rq 5hvlvwlyh 6kruwwr9 && +dug 6kruwwr9 && 6kruwwr9 && , 287 9 287 9 &6b',6 9 2/ 9 287 !9 2/ w '67.rq $*9 7 - hyroxwlrqlq 2yhuordgru6kruwwr*1' , /lp+ ! 3rzhu/lplwdwlrq 6hoiolplwdwlrqriidvwwkhupdowudqvlhqwv ,1387 7 - , 287 7 -b67$57 7 5 7 76' 7 +<67 , /lp/ $*9
docid17362 rev 6 21/37 VND5E006ASP-E electrical specifications 36 2.5 electrical characteristics curves figure 17. off-state output current figure 18. high level input current figure 19. input clamp voltage figure 20. input high level voltage figure 21. input low level voltage figure 22. input hysteresis voltage ,orii>q$@ 7f>?&@ $*9 ,lk>x$@ 7f>?&@ 9lq 9 $*9 $*9 9lfo>9@ 7f>?&@ ,lq p$ vih [v] 0 0.5 1 1.5 2 2.5 3 3.5 4 -50 -25 0 25 50 75 100 125 150 175 tc [c] a g00086v1 9lo>9@ 7f>?&@ $*9 $*9 9lk\vw>9@ 7f>?&@
electrical specifications VND5E006ASP-E 22/37 docid17362 rev 6 figure 23. on-state resistance vs t case figure 24. on-state resistance vs v cc figure 25. undervoltage shutdown figure 26. i limh vs t case figure 27. turn-on voltage slope figure 28. turn-off voltage slope $*9 5rq>p2kp@ 7f>?&@ ,rxw $ 9ff 9 $*9 5rq>p2kp@ 9ff>9@ 7f ?& 7f ?& 7f ?& 7f ?& $*9 9xvg>9@ 7f>?&@ $*9 ,olpk>$@ 7f>?&@ 9ff 9 $*9 g9rxwgw2q>9pv@ 7f>?&@ 9ff 9 5o $*9 g9rxwgw2ii>9pv@ 7f>?&@ 9ff 9 5o
docid17362 rev 6 23/37 VND5E006ASP-E electrical specifications 36 figure 29. cs_dis clamp voltage figure 30. low level cs_dis voltage figure 31. high level cs_dis voltage 9fvgfo>9@ 7f>?&@ ,lq p$ $*9 $*9 9fvgo>9@ 7f>?&@ $*9 9fvgk>9@ 7f>?&@
application information VND5E006ASP-E 24/37 docid17362 rev 6 3 application information figure 32. application schematic note: channel 2 has the same internal circuit as channel 1. 3.1 load dump protection d ld is necessary (voltage transient suppressor) if the load dump peak voltage exceeds the v cc max dc rating. the same applies if the device is subject to transients on the v cc line that are greater than the ones shown in the iso 7637-2 2004 (e) table. 3.2 mcu i/os protection when negative transients are present on the v cc line, the control pins are pulled negative to approximately -1.5 v. st suggests to insert a resistor (r prot ) in line to prevent the microcontroller i/o pins from latching-up. the value of these resistors is a compromise between the leakage current of microcontroller and the current required by the hsd i/os (input levels compatibility) with the latch-up limit of microcontroller i/os. equation 1 -v ccpeak /i latchup r prot (v oh c - v ih ) / i ihmax calculation example: for v ccpeak = -1.5 v and i latchup 20 ma; v oh c 4.5 v 75 r prot 240 k . recommended values: r prot = 10 k , c ext = 10 nf . 9 && *1' 287387 9 &6b',6 ,1387 5 surw ' og 5 6(16( &855(176(16( 0&8 9 & h[w 5 surw 5 surw 9 $*9
docid17362 rev 6 25/37 VND5E006ASP-E application information 36 3.3 current sense and diagnostic the current sense pin performs a double function (see figure 33: current sense and diagnostic ): ? current mirror of the load current in normal operation, delivering a current proportional to the load one according to a known ratio k x . the current i sense can be easily converted to a voltage v sense by means of an external resistor r sense . linearity between i out and v sense is ensured up to 5v minimum (see parameter v sense in table 9: current sense (8 v < vcc < 18 v) ). the current sense accuracy depends on the output current (refer to current sense electrical characteristics table 9: current sense (8 v < vcc < 18 v) ). ? diagnostic flag in fault conditions , delivering a fixed voltage v senseh up to a maximum current i senseh in case of the following fault conditions (refer to truth table ): ? power limitation activation ? overtemperature ? short to v cc in off-state ? open-load in off-state with additional external components. a logic level high on cs_dis pin sets at the same time all the current sense pins of the device in a high impedance state, thus disabling the current monitoring and diagnostic detection. this feature allows multiplexing of the microcontroller analog inputs by sharing of sense resistance and adc line among different devices. figure 33. current sense and diagnostic 0dlq026q 9 287q , /rii 5 6(16( 5 3527 7rx&$'& 5 38 9 38 3zub/lp 9 6(16( 38b&0' 2yhuwhpshudwxuh 2/2)) 9 2/ &855(17 6(16(q , 287 . ; , 6(16(+ 9 %$7 9 6(16(+ /rdg ,1387q 9 && *1' &6b',6 $*9
application information VND5E006ASP-E 26/37 docid17362 rev 6 3.3.1 short to v cc and off-state open-load detection short to v cc a short circuit between v cc and output is indicated by the relevant current sense pin set to v senseh during the device off-state. small or no current is delivered by the current sense during the on-state depending on the nature of the short circuit. off-state open-load with external circuitry detection of an open-load in off mode requires an external pull-up resistor r pu connecting the output to a positive supply voltage v pu . it is preferable v pu to be switched off during the module standby mode in order to avoid the overall standby current consumption to increase in normal conditions, i.e. when load is connected. for proper open-load detection in off-state, the external pull-up resistor must be selected according to the following formula: for the values of v olmin ,v olmax , and i l(off2) see table 10: open-load detection (8 v < vcc < 18 v) . v v r r i r r v r v ol pd pu off l pd pu pu pd on up pull out 4 max ) 2 ( _ = > + ? ? ? ? = ?
docid17362 rev 6 27/37 VND5E006ASP-E application information 36 3.4 maximum demagnetization energy (v cc = 13.5 v) figure 34. maximum turn-off current versus inductance note: values are generated with r l = 0 . in case of repetitive pulses, tjstart (at beginning of each demagnetization) of every pulse must not exceed the temperature specified above for curves a and b. c: t jstart = 125c repetitive pulse a: t jstart = 150c single pulse b: t jstart = 100c repetitive pulse 'hpdjqhwl]dwlrq 'hpdjqhwl]dwlrq 'hpdjqhwl]dwlrq w 9 ,1 , / $*9 ,$ /p+ 91'($63 6lqjoh3xovh 5hshwlwlyhsxovh7mvwduw ?& 5hshwlwlyhsxovh7mvwduw ?& $*9
package and pcb thermal data VND5E006ASP-E 28/37 docid17362 rev 6 4 package and pcb thermal data 4.1 powerso-16 thermal data figure 35. powerso-16 pc board (1) 1. layout condition of r th and z th measurements (pcb: double layer, thermal vias, fr4 area= 77mm x 86mm, pcb thickness=1.6mm, cu thickness=70 m (front and back side), copper areas: from minimum pad lay-out to 8cm 2 ). figure 36. r thj-amb vs pcb copper area in open box free air condition (one channel on) $*9 57+mbdpe?&: 3&%&xkhdwvlqnduhdfpa 57+mbdpeyv&xkhdwvlqnduhd 57+mdpe $*9
docid17362 rev 6 29/37 VND5E006ASP-E package and pcb thermal data 36 figure 37. powerso-16 thermal impedanc e junction ambient single pulse (one channel on) figure 38. thermal fitting model of a double channel hsd in powerso-16 (1) 1. the fitting model is a semplified thermal tool and is valid for transient evolutions where the embedded protections (power limitation or thermal cyc ling during thermal shutdown) are not triggered. 100 zth (c/w) cu=8 cm2 100 zth (c/w) cu=8 cm2 cu=2 cm2 cu=foot print 10 100 zth (c/w) cu=8 cm2 cu=2 cm2 cu=foot print 1 10 100 zth (c/w) cu=8 cm2 cu=2 cm2 cu=foot print 1 10 100 zth (c/w) cu=8 cm2 cu=2 cm2 cu=foot print 0.1 1 10 100 0.0001 0.001 0.01 0.1 1 10 100 1000 zth (c/w) ti ( ) cu=8 cm2 cu=2 cm2 cu=foot print 0.1 1 10 100 0.0001 0.001 0.01 0.1 1 10 100 1000 zth (c/w) time (s) cu=8 cm2 cu=2 cm2 cu=foot print a g00104v1 $*9
package and pcb thermal data VND5E006ASP-E 30/37 docid17362 rev 6 equation 2: pulse calculation formula table 15. thermal parameters area/island (cm 2 )footprint28 r1=r7 (c/w) 0.05 r2=r8 (c/w) 0.4 r3 (c/w) 1 r4 (c/w) 7 r5 (c/w) 12 10 8 r6 (c/w) 22 18 12 c1=c7 (w.s/c) 0.01 c2=c8 (w.s/c) 0.1 c3 (w.s/c) 1 c4 (w.s/c) 2 c5 (w.s/c) 3 4 7 c6 (w.s/c) 5 6 12 z th r th z thtp 1 ? () + ? = where t p t ? =
docid17362 rev 6 31/37 VND5E006ASP-E package information 36 5 package information 5.1 ecopack ? packages in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark. 5.2 powerso-16 mechanical data figure 39. powerso-16 package dimensions $*9
package information VND5E006ASP-E 32/37 docid17362 rev 6 table 16. powerso-16 mechanical data dim. mm min. typ. max. a1 0 0.05 0.1 a2 3.4 3.5 3.6 a3 1.2 1.3 1.4 a4 0.15 0.2 0.25 a0.2 b 0.27 0.35 0.43 c 0.23 0.27 0.32 d9.4 9.5 9.6 d1 7.4 7.5 7.6 d 0 0.05 0.1 e (1) 13.85 14.1 14.35 e1 9.3 9.4 9.5 e2 7.3 7.4 7.5 e3 5.9 6.1 6.3 e 0.8 e1 5.6 f0.5 g1.2 l0.8 1 1.1 r1 0.25 r2 0.8 t 2 5 8 t1 6 (typ.) t2 10 (typ.)
docid17362 rev 6 33/37 VND5E006ASP-E package information 36 5.3 packing information figure 40. powerso-16 tube shipment (no suffix) figure 41. powerso-16 tape and reel shipment (suffix ?tr?) $ % & $*9 all dimensions are in mm. base q.ty 50 bulk q.ty 1000 a 4.9 b 17.2 c ( 0.1) 0.8 tube length ( 0.5) 532 reel dimensions all dimensions are in mm. base q.ty 600 bulk q.ty 600 a (max) 330 b (min) 1.5 c ( 0.2) 13 f 20.2 g (+ 2 / -0) 24.4 n (min) 60 t (max) 30.4 tape dimensions according to electronic industries association (eia) standard 481 rev. a, feb. 1986 all dimensions are in mm. tape width w 24 tape hole spacing p0 ( 0.1) 4 component spacing p 24 hole diameter d (+ 0.1/-0) 1.5 hole diameter d1 (min) 1.5 hole position f ( 0.05) 11.5 compartment depth k (max) 6.5 hole spacing p1 ( 0.1) 2 top cover tape end start no components no components components 500mm min 500mm min empty components pockets saled with cover tape. user direction of feed a g00108v1
package information VND5E006ASP-E 34/37 docid17362 rev 6 figure 42. powerso-16 suggested pad layout $*9
docid17362 rev 6 35/37 VND5E006ASP-E order codes 36 6 order codes table 17. device summary package order codes tube tape and reel powerso-16 VND5E006ASP-E vnd5e006asptr-e
revision history VND5E006ASP-E 36/37 docid17362 rev 6 7 revision history table 18. document revision history date revision changes 18-apr-2010 1 initial release. 02-jul-2010 2 updated features list. 21-jul-2010 3 updated table 9: current sense (8 v < vcc < 18 v) . 19-jan-2011 4 added section 3.4: maximum demagnetization energy (vcc = 13.5 v) table 3: absolute maximum ratings : ?e max : updated value and test condition table 4: thermal data ? added r thj-case row 19-sep-2013 5 updated disclaimer. 28-oct-2013 6 updated footnote 2 into the table 12: electrical transient requirements (part 1/3) and table 13: electrical transient requirements (part 2/3) .
docid17362 rev 6 37/37 VND5E006ASP-E 37 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a particular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. st products are not designed or authorized for use in: (a) safety critical applications such as life supporting, active implanted devices or systems with product functional safety requirements; (b) aeronautic applications; (c) automotive applications or environments, and/or (d) aerospace applications or environments. where st products are not designed for such use, the purchaser shall use products at purchaser?s sole risk, even if st has been informed in writing of such usage, unless a product is expressly designated by st as being intended for ?automotive, automotive safety or medical? industry domains according to st product design specifications. products formally escc, qml or jan qualified are deemed suitable for use in aerospace by the corresponding governmental agency. resale of st products with provisions different from the statem ents and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or register ed trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2013 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - swed en - switzerland - united kingdom - united states of america www.st.com

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